Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), conventionally includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile conventionally includes both programmable interconnect and programmable logic. The programmable interconnect conventionally includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic conventionally may be programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external non-volatile memory, such as flash memory or read-only memory) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is conventionally stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (“programming”) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Conventionally, embedded processors are designed apart from the PLDs. Such embedded processors are generally not specifically designed for implementation in PLDs, and thus such embedded processors may have operating frequencies that significantly exceed a maximum operating frequency of programmable logic of such PLDs. Moreover, parameters designed into the embedded processors, such as latency, transistor gate delay, data throughput, and the like, may be assumed to be present in the environment to which the embedded processors are to be coupled. Thus even though a PLD may include an embedded processor, such one or more operating parameters of the embedded processor may be substantially disparate from those of programmable logic of the PLD.
For purposes of clarity by way of example and not limitation, an FPGA with an embedded processor is described; however, it should be appreciated that other PLDs, as well as other integrated circuits with programmable logic or other circuitry fabric with less performance than the embedded processor, may likewise be used in accordance with the following description.
Performance of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) coupled to an embedded processor may be significantly limited by disparity between operating parameters of the FPGA fabric and those of the embedded processor. Thus, if, as in the past, embedded processor interfaces such as processor local bus (“PLB”) interfaces are brought directly out to FPGA fabric, disparity between respective operating parameters of the embedded processor and the FPGA fabric is a significant limitation with respect to overall performance. For example, operations between a memory controller instantiated in FPGA fabric and an embedded processor have heretofore been significantly bottlenecked due to having to wait on the slower memory controller.
Alternatively, to enhance performance, a memory controller instantiated in FPGA fabric may be hardened or provided as an ASIC core coupled to the embedded processor. By hardening a circuit instantiated in FPGA fabric, it is generally meant replacing or bypassing configuration memory cells with hardwired or dedicated connections. Even though the example of a memory controller is used, it should be understood that other peripherals may be hardened or provided as ASIC cores for coupling to an embedded processor. However, as the memory controller or peripheral ASIC or hardened core is not configurable, this reduces overall flexibility. For purposes of clarity by way of example and not limitation, ASIC cores are described even though hardened cores instantiated in FPGA fabric may also be used.
Semiconductor processes and semiconductor process integration rules (“semiconductor process design rules”) associated with ASICs are generally more challenging than those associated with FPGAs, and thus yield for such ASICs may be relatively low as compared to yield of FPGAs of the same size. FPGAs, which may have a larger and longer run rate than ASICs, may employ semiconductor process design rules that are less aggressive but are more conducive to a higher die per wafer yield than that of ASICs.
It should be understood that an FPGA manufactured with an ASIC core uses FPGA semiconductor process design rules. Thus, ASIC cores manufactured in FPGAs perform worse than such ASIC cores manufactured as standalone ASICs using more aggressive ASIC semiconductor process design rules. Thus, manufacturing FPGAs with ASIC cores conventionally will not achieve competitive performance with standalone ASICs.
For FPGAs provided with ASIC cores that take the place of some FPGA fabric resources, users conventionally are locked into the particular offering of ASIC core memory controllers or peripherals, and have less flexibility of design due to fewer FPGA fabric resources for implementing their circuit design. This loss of flexibility combined with the fact that such ASIC core memory controllers or peripherals implemented in FPGA fabric may make FPGAs less attractive to users.
Accordingly, it would be desirable and useful to enhance performance of FPGAs without a significant loss of design flexibility associated with adding an ASIC core.